1. Field of the Invention
The present invention generally relates to field effect transistors suitable for use in high density integrated circuits and, more particularly to field effect transistors of extremely small size with reduced short channel effects formed on silicon-on-insulator (SOT) and double SOI substrates.
2. Description of the Prior Art
The potential for increased performance and functionality of integrated circuits by increased proximity of devices has provided a strong incentive to increase integration density to decrease length of signal propagation paths, and increase the number of devices which can be formed on a single chip of a given size. Reduction of signal path length reduces interconnection resistance and capacitance and allows reduction of signal propagation time as well as susceptibility to capacitive or inductive coupling of noise. Such reductions in interconnect capacitance must also be accompanied by reductions in device dimensions both to reduce parasitic capacitances which reduce switching speed and to allow optimal reduction of interconnect length consistent with suitable dimensions for isolation structures. Accordingly, lithographic techniques have become very sophisticated and can produce minimum feature sizes of a fraction of a micrometer.
In general, while semiconductor processing techniques have been developed to form structures having dimensions much smaller than can be resolved by lithographic exposure techniques, at least one lithographic exposure is necessary to define the location and general dimensions of a device or other structure. However, while some structures can be formed at such small sizes, others cannot and adjustments in operating parameters are often required. In other cases, difficulty in scaling semiconductor structures when seeking to exploit newly developed lithographic capabilities may be the principal limiting factor in the successful reduction of active device dimensions or limit the performance which can be obtained from an active device of a given size at the limit of lithographic resolution. Some active device structures simply do not scale well to smaller sizes.
For example, in field effect transistors, short channel effects which cause leakage and reduction in resistance differential between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states have been recognized for many years as the conduction channel length was reduced in transistor designs. This problem led to the development of lightly doped drain structures, now more generally referred to as extension implants since optimal impurity concentrations can be substantial while the dimensions thereof are generally very small. Also, gate to substrate capacitance has limited performance and led to so-called xe2x80x9chaloxe2x80x9d implants to increase the impurity concentration gradient in the substrate below the gate structure. Both of these structures require that the impurity concentration be well-controlled and the concentration gradients be very steep, particularly in devices of small size.
In general, impurities are placed in desired locations by implantation which can be controlled to sub-lithographic dimensions by known techniques. However, implantation must be followed by a closely controlled heat treatment or annealing process to repair lattice damage from the implantation and to activate the impurity by incorporation in the lattice structure. Such heat treatment also causes diffusion of the impurity which cannot be avoided and the implant location must often be adjusted to compensate for the diffusion so that the final impurity location will be as intended. The mechanics of diffusion are inherent material properties and are well-understood to depend upon the materials (and the microstructure thereof), temperature, time and impurity concentration gradient. Many state-of-the-art semiconductor structure designs therefore have a heat budget which cannot be exceeded without compromise of the intended electrical properties of the device.
Viewed another way, a given amount of heat treatment required following impurity implantation to repair lattice damage and activate the impurity will inevitably lead to a reduction in the steepness of impurity concentration gradient while decreased size of active semiconductor devices, and field effect transistors, in particular, makes the steepness of impurity concentration gradients much more critical in smaller devices in order to obtain optimal device performance. This can be understood from the fact that a scaling of a transistor to smaller dimensions would require increase in the impurity concentration gradient while that increase in concentration gradient may not be possible or available consistent with annealing after an impurity implantation and other device impurity concentration requirements.
To obtain high performance and consistency of conduction characteristics of transistors formed on a chip or wafer, silicon-on-insulator substrates have been employed in recent years, largely enabled by the extremely high quality of monocrystalline silicon which is produced in a relatively thin surface layer. However, certain electrical characteristics and device structure designs may be complicated by the placement of the high quality surface layer on an insulator which insulates it from the bulk or handling substrate provided to reduce fragility of the wafer or chip. In particular, deep structures may be difficult to form and process windows may be significantly restricted.
It is therefore an object of the present invention to provide a field effect transistor structure of extremely small size with improved performance and reduced short channel effects on SOI and double SOI wafers and chips.
It is another object of the invention to provide a technique for developing high impurity concentration gradients for halo and extension structures in field effect transistors on SOI and double SOI wafers or chips, particularly when of small size.
It is a further object of the invention to provide high and improved performance of field effect transistors formed at sub-lithographic dimensions on SOI and double SOI wafers or chips.
It is yet another object of the present invention to provide enhanced performance and electrical characteristics similar to dual gate transistors utilizing double SOI.
In order to accomplish these and other objects of the invention, a method of forming a semiconductor device is provided including steps of forming a recess in a monocrystalline layer on an insulator and adjacent a stud defining a transistor location, depositing polycrystalline material in the recess, implanting an impurity in the polycrystalline material, and diffusing the impurity along grain boundaries in the polycrystalline material into said monocrystalline material whereby rapid diffusion in the polysilicon relative to the diffusion in the monocrystalline material forms a steep impurity concentration gradient for halo and/or extension impurity structures.
In accordance with another aspect of the invention, a semiconductor device is provided including sidewalls formed on the interior of an aperture in a polycrystalline semiconductor material and adjacent monocrystalline semiconductor material on an insulator layer underlying the aperture, a gate structure formed within the aperture, and an impurity concentration gradient extending below the gate structure.